The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 31, 2024

Filed:

Dec. 23, 2020
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Jayesh Gaur, Bangalore, IN;

Adarsh Chauhan, Bangalore, IN;

Vinodh Gopal, Westborough, MA (US);

Vedvyas Shanbhogue, Austin, TX (US);

Sreenivas Subramoney, Bangalore, IN;

Wajdi Feghali, Boston, MA (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 12/0811 (2016.01); G06F 9/38 (2018.01); G06F 12/0862 (2016.01); G06F 12/0895 (2016.01);
U.S. Cl.
CPC ...
G06F 12/0811 (2013.01); G06F 9/3802 (2013.01); G06F 9/3836 (2013.01); G06F 12/0862 (2013.01); G06F 12/0895 (2013.01); G06F 2212/401 (2013.01);
Abstract

Methods and apparatus relating to an instruction and/or micro-architecture support for decompression on core are described. In an embodiment, decode circuitry decodes a decompression instruction into a first micro operation and a second micro operation. The first micro operation causes one or more load operations to fetch data into one or more cachelines of a cache of a processor core. Decompression Engine (DE) circuitry decompresses the fetched data from the one or more cachelines of the cache of the processor core in response to the second micro operation. Other embodiments are also disclosed and claimed.


Find Patent Forward Citations

Loading…