The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 31, 2024

Filed:

Oct. 26, 2022
Applicant:

Nxp Usa, Inc., Austin, TX (US);

Inventors:

Alexander Hoefler, Austin, TX (US);

Jeffrey Stump, Lexington, TX (US);

Assignee:

NXP USA, Inc., Austin, TX (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G01R 31/3185 (2006.01); G01R 31/317 (2006.01); G11C 7/10 (2006.01); G11C 29/04 (2006.01); G11C 29/32 (2006.01);
U.S. Cl.
CPC ...
G01R 31/318541 (2013.01); G01R 31/31722 (2013.01); G01R 31/318558 (2013.01); G11C 7/106 (2013.01); G11C 7/1087 (2013.01); G11C 2029/0401 (2013.01); G11C 29/32 (2013.01); G11C 2029/3202 (2013.01);
Abstract

A system includes test control circuitry and a memory. The memory includes a memory array, a pre-decode circuit, and a plurality of address latches. Each address latch of the plurality of address latches is configured to operate in a scan chain of a plurality of scan chains for scan testing. A first set of the plurality of address latches each has a data input coupled to a corresponding address pin of the first memory and each has an output coupled to the pre-decode circuit. A second set of the plurality of address latches, mutually exclusive of the first set, each has a data input coupled to a data input of at least one latch in the first set of the plurality of latches and each is configured to not provide any input to the pre-decode circuit.


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