The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 24, 2024

Filed:

Jul. 31, 2023
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu, TW;

Inventor:

Chung-Yen Chou, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10N 70/00 (2023.01); H10B 63/00 (2023.01);
U.S. Cl.
CPC ...
H10N 70/063 (2023.02); H10B 63/30 (2023.02); H10N 70/021 (2023.02); H10N 70/826 (2023.02); H10N 70/841 (2023.02); H10N 70/8833 (2023.02); G11C 2213/52 (2013.01);
Abstract

An integrated chip comprising a memory cell is provided. The memory cell is disposed over a substrate and comprises a data storage layer between a top metal layer and a bottom metal layer. An etch stop layer overlies the top metal layer. An upper dielectric layer overlies the etch stop layer. Outer sidewalls of the etch stop layer, outer sidewalls of the upper dielectric layer, and outer sidewalls of the top metal layer are aligned. A top electrode overlies the memory cell. The top electrode directly contacts inner sidewalls of the top metal layer, inner sidewalls of the etch stop layer, and inner sidewalls of the upper dielectric layer.


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