The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 24, 2024

Filed:

Jul. 28, 2022
Applicant:

Changxin Memory Technologies, Inc., Hefei, CN;

Inventor:

Yi Tang, Hefei, CN;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/265 (2006.01); H01L 21/768 (2006.01); H01L 21/822 (2006.01); H10B 12/00 (2023.01);
U.S. Cl.
CPC ...
H01L 21/2652 (2013.01); H01L 21/7688 (2013.01); H01L 21/8221 (2013.01); H10B 12/482 (2023.02); H10B 12/488 (2023.02);
Abstract

Embodiments of the present disclosure provide a semiconductor structure and a manufacturing method thereof. The method includes: providing a substrate, wherein the substrate includes a word line region, a bit line region, and a capacitive region arranged adjacently; forming a first stacked structure that covers a surface of the substrate, wherein the first stacked structure includes a first sacrificial layer located on the surface of the substrate and a first semiconductor layer located on a surface of the first sacrificial layer; forming a second stacked structure that covers a surface of the first stacked structure, wherein the second stacked structure includes a second sacrificial layer located on the surface of the first stacked structure and a second semiconductor layer located on a surface of the second sacrificial layer; and performing an ion implantation on the first semiconductor layer and the second semiconductor layer.


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