The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 24, 2024
Filed:
Apr. 27, 2023
Applicant:
Silicon Storage Technology, Inc., San Jose, CA (US);
Inventors:
Hieu Van Tran, San Jose, CA (US);
Stanley Hong, San Jose, CA (US);
Stephen Trinh, San Jose, CA (US);
Thuan Vu, San Jose, CA (US);
Steven Lemke, Boulder Creek, CA (US);
Vipin Tiwari, Dublin, CA (US);
Nhan Do, Saratoga, CA (US);
Assignee:
SILICON STORAGE TECHNOLOGY, INC., San Jose, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 16/10 (2006.01); G06N 3/065 (2023.01); G11C 11/56 (2006.01); G11C 16/04 (2006.01); G11C 16/14 (2006.01); G11C 16/34 (2006.01);
U.S. Cl.
CPC ...
G11C 16/10 (2013.01); G06N 3/065 (2023.01); G11C 11/5628 (2013.01); G11C 16/0425 (2013.01); G11C 16/0433 (2013.01); G11C 16/14 (2013.01); G11C 16/3459 (2013.01);
Abstract
In one example, a method comprises determining a program resolution current value; and setting levels for a programming operation of a plurality of non-volatile memory cells in a neural network array such that a delta current between levels of each pair of adjacent cells in the plurality is a multiple of the program resolution current value.