The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 24, 2024

Filed:

Dec. 20, 2019
Applicant:

Ampere Computing Llc, Santa Clara, CA (US);

Inventors:

Jonathan Christopher Perry, Santa Clara, CA (US);

Jason Anthony Bessette, Santa Clara, CA (US);

Sean Philip Mirkes, Santa Clara, CA (US);

Jacob Daniel Morgan, Santa Clara, CA (US);

John Saint Tran, Santa Clara, CA (US);

Assignee:

Ampere Computing LLC, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 9/30 (2018.01); G06F 9/38 (2018.01);
U.S. Cl.
CPC ...
G06F 9/30043 (2013.01); G06F 9/384 (2013.01);
Abstract

Aspects disclosed include hardware micro-fused memory (e.g., load and store) operations. In one aspect, a hardware micro-fused memory operation is a single atomic memory operation performed using a plurality of data register operands, for example a load pair or store pair operation. The load pair or store pair operation is treated as two separate operations for purposes of renaming, but is scheduled as a single micro-operation having two data register operands. The load or store pair operation is then performed atomically.


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