The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 24, 2024

Filed:

Apr. 26, 2021
Applicant:

Micron Technology, Inc., Boise, ID (US);

Inventors:

Bryan Hornung, Plano, TX (US);

Tony M. Brewer, Plano, TX (US);

Douglas Vanesko, Dallas, TX (US);

Patrick Estep, Rowlett, TX (US);

Assignee:

Micron Technology, Inc., Boise, ID (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 13/16 (2006.01); G01S 7/41 (2006.01); G01S 13/90 (2006.01); G01S 13/933 (2020.01); G06F 9/30 (2018.01); G06F 9/38 (2018.01); G06N 20/00 (2019.01);
U.S. Cl.
CPC ...
G06F 13/1668 (2013.01); G01S 7/41 (2013.01); G01S 13/9021 (2019.05); G01S 13/933 (2020.01); G06F 9/3001 (2013.01); G06F 9/3887 (2013.01); G06N 20/00 (2019.01);
Abstract

Linear interpolation is performed within a memory system. The memory system receives a floating-point point index into an integer-indexed memory array. The memory system accesses the two values of the two adjacent integer indices, performs the linear interpolation, and provides the resulting interpolated value. In many system architectures, the critical limitation on system performance is the data transfer rate between memory and processing elements. Accordingly, reducing the amount of data transferred improves overall system performance and reduces power consumption.


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