The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 24, 2024

Filed:

Dec. 01, 2022
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Luis Kida, Beaverton, OR (US);

Siddhartha Chhabra, Portland, OR (US);

Reshma Lal, Portland, OR (US);

Pradeep M. Pappachan, Tualatin, OR (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H04L 29/06 (2006.01); G06F 9/38 (2018.01); G06F 9/455 (2018.01); G06F 12/0802 (2016.01); G06F 12/14 (2006.01); G06F 21/57 (2013.01); G06F 21/60 (2013.01); G06F 21/64 (2013.01); G06F 21/76 (2013.01); G06F 21/79 (2013.01); H04L 9/06 (2006.01); H04L 9/08 (2006.01); H04L 9/32 (2006.01); H04L 41/046 (2022.01); H04L 41/28 (2022.01);
U.S. Cl.
CPC ...
G06F 12/1408 (2013.01); G06F 9/3877 (2013.01); G06F 9/45558 (2013.01); G06F 12/0802 (2013.01); G06F 21/57 (2013.01); G06F 21/602 (2013.01); G06F 21/606 (2013.01); G06F 21/64 (2013.01); G06F 21/76 (2013.01); G06F 21/79 (2013.01); H04L 9/0631 (2013.01); H04L 9/0637 (2013.01); H04L 9/083 (2013.01); H04L 9/0838 (2013.01); H04L 9/0844 (2013.01); H04L 9/085 (2013.01); H04L 9/0891 (2013.01); H04L 9/321 (2013.01); H04L 9/3215 (2013.01); H04L 9/3226 (2013.01); H04L 9/3268 (2013.01); H04L 9/3278 (2013.01); H04L 41/046 (2013.01); H04L 41/28 (2013.01); G06F 2009/45591 (2013.01); G06F 2009/45595 (2013.01);
Abstract

Technologies for secure I/O data transfer include a computing device having a processor and an accelerator. Each of the processor and the accelerator includes a memory encryption engine. The computing device configures both memory encryption engines with a shared encryption key and transfers encrypted data from a source component to a destination component via an I/O link. The source may be processor and the destination may be the accelerator or vice versa. The computing device may perform a cryptographic operation with one of the memory encryption engines and bypass the other memory encryption engine. The computing device may read encrypted data from a memory of the source, bypass the source memory encryption engine, and transfer the encrypted data to the destination. The destination may receive encrypted data, bypass the destination memory encryption engine, and store the encrypted data in a memory of the destination. Other embodiments are described and claimed.


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