The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 24, 2024

Filed:

Nov. 18, 2021
Applicant:

Arm Limited, Cambridge, GB;

Inventors:

Joseph Michael Pusdesris, Austin, TX (US);

Klas Magnus Bruce, Austin, TX (US);

Jamshed Jalal, Austin, TX (US);

Dimitrios Kaseridis, Austin, TX (US);

Gurunath Ramagiri, Austin, TX (US);

Ho-Seop Kim, Austin, TX (US);

Andrew John Turner, Cambridge, GB;

Rania Hussein Hassan Mameesh, Cambridge, GB;

Assignee:

Arm Limited, Cambridge, GB;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 12/126 (2016.01); G06F 12/0811 (2016.01);
U.S. Cl.
CPC ...
G06F 12/126 (2013.01); G06F 12/0811 (2013.01);
Abstract

Aspects of the present disclosure relate to an apparatus comprising processing circuitry, first cache circuitry and second cache circuitry, wherein the second cache circuitry has an access latency higher than an access latency of the first cache circuitry. The second cache circuitry is responsive to receiving a request for data stored within the second cache circuitry to identify said data as pseudo-invalid data and provide said data to the first cache circuitry. The second cache circuitry is responsive to receiving an eviction indication, indicating that the first cache circuitry is to evict said data, to, responsive to determining that said data has not been modified since said data was provided to the first cache circuitry, identify said pseudo-invalid data as valid data.


Find Patent Forward Citations

Loading…