The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 24, 2024

Filed:

Jul. 30, 2021
Applicant:

Marvell Asia Pte, Ltd., Singapore, SG;

Inventors:

Ulf Hanebutte, Gig Harbor, WA (US);

Harri Hakkarainen, Los Gatos, CA (US);

Senad Durakovic, Palo Alto, CA (US);

Chien-Chun Chou, Morgan Hill, CA (US);

Assignee:

Marvell Asia Pte Ltd, Singapore, SG;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 11/36 (2006.01); G06F 8/41 (2018.01); G06F 11/34 (2006.01); G06N 20/00 (2019.01);
U.S. Cl.
CPC ...
G06F 11/3664 (2013.01); G06F 8/41 (2013.01); G06F 11/3466 (2013.01); G06N 20/00 (2019.01);
Abstract

A new approach is proposed to support correlating high-level code with low-level instructions of an application running on a hardware. A compiler that compiles a high-level function in the high-level code of the application into a set of low-level instructions to be executed on the hardware is configured to utilize one or more reserved fields of the set of low-level instructions to incorporate one or more IDs and an actionable item. The IDs are mapped to the high-level function, wherein such mapping is programmable by the compiler. Based on the mapped IDs and the actionable item incorporated in the set of the low-level instructions, the runtime performance of the application on the hardware can be monitored and profiled and issues related to the high-level code of the application can be identified for debugging purposes.


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