The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 24, 2024

Filed:

Dec. 11, 2020
Applicant:

Exo Imaging, Inc., Redwood City, CA (US);

Inventors:

Brian Bircumshaw, Oakland, CA (US);

Sandeep Akkaraju, Wellesley, MA (US);

Assignee:

Exo Imaging, Inc., Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
B06B 1/00 (2006.01); B06B 1/06 (2006.01); G01S 7/52 (2006.01); G01S 15/89 (2006.01); H10N 30/073 (2023.01); H10N 30/088 (2023.01); H10N 30/80 (2023.01); H10N 30/853 (2023.01); H10N 30/87 (2023.01);
U.S. Cl.
CPC ...
B06B 1/0622 (2013.01); G01S 7/52019 (2013.01); G01S 7/52023 (2013.01); G01S 15/8906 (2013.01); H10N 30/073 (2023.02); H10N 30/088 (2023.02); H10N 30/802 (2023.02); H10N 30/8554 (2023.02); H10N 30/875 (2023.02); H10N 30/877 (2023.02); B06B 2201/76 (2013.01);
Abstract

The present disclosure provides methods to integrate piezoelectric micromachined ultrasonic transducer (pMUT) arrays with an application-specific integrated circuit (ASIC) using thermocompression or eutectic/solder bonding. In an aspect, the present disclosure provides a device comprising a first substrate and a second substrate, the first substrate comprising a pMUT array and the second substrate comprising an electrical circuit, wherein the first substrate and the second substrate are bonded together using thermocompression, wherein any set of individual PMUTs of PMUT array is addressable. In another aspect, the present disclosure provides a device comprising a first substrate and a second substrate, the first substrate comprising a pMUT array and the second substrate comprising an electrical circuit, wherein the first substrate and the second substrate are bonded together using eutectic or solder bonding, wherein any set of individual PMUTs of the PMUT array is addressable.


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