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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 12170280 B1

PDFFull Text
Date of Patent:
Dec. 17, 2024

Filed:

Nov. 29, 2023

Method of manufacturing gate structure and method of manufacturing fin-field effect transistor

Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Ji-Cheng Chen, Hsinchu, TW;

Ching-Hwanq Su, Tainan, TW;

Kuan-Ting Liu, Hsinchu, TW;

Shih-Hang Chiu, Taichung, TW;

Assignee:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Attorney:

JCIPRNET

Primary Examiner:

Evren Seven

Int. Cl.
CPC ...
H01L 27/088 (2006.01); H01L 21/02 (2006.01); H01L 21/28 (2006.01); H01L 21/285 (2006.01); H01L 21/3105 (2006.01); H01L 21/762 (2006.01); H01L 21/8234 (2006.01); H01L 29/06 (2006.01); H01L 29/423 (2006.01); H01L 29/49 (2006.01); H01L 29/51 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01);
U.S. Cl.
CPC ...
H01L 27/0886 (2013.01); H01L 21/02205 (2013.01); H01L 21/02211 (2013.01); H01L 21/28088 (2013.01); H01L 21/28556 (2013.01); H01L 21/76224 (2013.01); H01L 21/823431 (2013.01); H01L 21/823437 (2013.01); H01L 21/823462 (2013.01); H01L 21/823481 (2013.01); H01L 29/0649 (2013.01); H01L 29/42372 (2013.01); H01L 29/4966 (2013.01); H01L 29/513 (2013.01); H01L 29/66545 (2013.01); H01L 21/02532 (2013.01); H01L 21/02579 (2013.01); H01L 21/0262 (2013.01); H01L 21/31053 (2013.01); H01L 29/517 (2013.01); H01L 29/7848 (2013.01);
Abstract

A method of manufacturing a gate structure includes at least the following steps. A gate dielectric layer is formed. A work function layer is deposited on the gate dielectric layer. A barrier layer is formed on the work function layer. A metal layer is deposited on the barrier layer to introduce fluorine atoms into the barrier layer. The barrier layer is formed by at least the following steps. A first TiN layer is formed on the work function layer. A top portion of the first TiN layer is converted into a trapping layer, and the trapping layer includes silicon atoms or aluminum atoms. A second TiN layer is formed on the trapping layer.

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