The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 17, 2024

Filed:

Jul. 31, 2023
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Shao-Lun Chien, Hsinchu, TW;

Pin-Dai Sue, Hsinchu, TW;

Li-Chun Tien, Hsinchu, TW;

Ting-Wei Chiang, Hsinchu, TW;

Ting Yu Chen, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 30/398 (2020.01); G03F 1/36 (2012.01); G06F 30/392 (2020.01); G06F 30/394 (2020.01);
U.S. Cl.
CPC ...
G06F 30/398 (2020.01); G03F 1/36 (2013.01); G06F 30/392 (2020.01); G06F 30/394 (2020.01);
Abstract

A transmission gate structure includes first and second PMOS transistors positioned in a first active area, first and second NMOS transistors positioned in a second active area parallel to the first active area, and four metal segments parallel to the active areas. A first metal segment overlies the first active area, a fourth metal segment overlies the second active area, and second and third metal segments are a total of two metal segments positioned between the first and fourth metal segments. A first conductive path connects gates of the first PMOS and NMOS transistors, a second conductive path connects gates of the second PMOS and NMOS transistors, a third conductive path connects a source/drain (S/D) terminal of each of the first and second PMOS transistors and first and second NMOS transistors and includes a first conductive segment extending across at least three of the four metal segments.


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