The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 17, 2024

Filed:

Feb. 15, 2022
Applicant:

Taiwan Semiconductor Manufacturing Company Ltd., Hsinchu, TW;

Inventors:

Shang Hsien Yang, Hsinchu, TW;

Chung-Chieh Yang, Hsinchu County, TW;

Yung-Chow Peng, Hsinchu, TW;

Chih-Chiang Chang, Taipei, TW;

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G01R 31/319 (2006.01); G01R 31/317 (2006.01); G01R 31/3183 (2006.01); H03K 3/037 (2006.01); H03K 5/26 (2006.01);
U.S. Cl.
CPC ...
G01R 31/31922 (2013.01); G01R 31/31725 (2013.01); G01R 31/318328 (2013.01); G01R 31/3191 (2013.01); H03K 3/037 (2013.01); H03K 5/26 (2013.01);
Abstract

A delay measurement system and a measurement method are provided. The delay measurement system includes a delay control device and a comparator. The delay control device is configured to generate a second signal in response to a first signal, wherein a rising edge of the second signal delays a first delay time with respect to a rising edge of the first signal, and the first delay time is controlled in response to an output signal of a comparator. The comparator is configured to compare the first delay time with a second delay time and output the output signal, wherein a rising edge of a third signal delays the second delay time with respect to the rising edge of the first signal, and the third signal is generated by a device under test (DUT) in response to the first signal.


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