The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 10, 2024

Filed:

May. 28, 2021
Applicant:

Nxp Usa, Inc., Austin, TX (US);

Inventors:

David Cobb Burdeaux, Tempe, AZ (US);

Joseph Gerard Schultz, Wheaton, IL (US);

Kimberly Foxx, Phoenix, AZ (US);

Assignee:

NXP USA, Inc., Austin, TX (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H03F 3/21 (2006.01); H01L 23/66 (2006.01); H03F 1/02 (2006.01); H03F 1/52 (2006.01); H03F 1/56 (2006.01); H03F 3/195 (2006.01); H03F 3/24 (2006.01);
U.S. Cl.
CPC ...
H03F 3/195 (2013.01); H01L 23/66 (2013.01); H03F 1/0227 (2013.01); H03F 1/523 (2013.01); H03F 1/565 (2013.01); H03F 3/245 (2013.01); H01L 2223/6611 (2013.01); H01L 2223/6655 (2013.01); H03F 2200/441 (2013.01); H03F 2200/451 (2013.01);
Abstract

An amplifier includes a semiconductor die and a substrate that is distinct from the semiconductor die. The semiconductor die includes a first RF signal input terminal, a first RF signal output terminal, and a transistor. The transistor has a control terminal electrically coupled to the first RF signal input terminal, and a current-carrying terminal electrically coupled to the first RF signal output terminal. The substrate includes a second RF signal input terminal, a second RF signal output terminal, circuitry coupled between the second RF signal input terminal and the second RF signal output terminal, and an electrostatic discharge (ESD) protection circuit. The amplifier also includes a connection electrically coupled between the ESD protection circuit and the control terminal of the transistor. The substrate may be another semiconductor die (e.g., with a driver transistor and/or impedance matching circuitry) or an integrated passive device.


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