The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 10, 2024

Filed:

Sep. 11, 2020
Applicant:

Macom Technology Solutions Holdings, Inc., Lowell, MA (US);

Inventors:

Basim Noori, San Jose, CA (US);

Marvin Marbell, Morgan Hill, CA (US);

Scott Sheppard, Chapel Hill, NC (US);

Kwangmo Chris Lim, San Jose, CA (US);

Alexander Komposch, Morgan Hill, CA (US);

Qianli Mu, San Jose, CA (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/047 (2006.01); H01L 23/00 (2006.01); H01L 23/31 (2006.01); H01L 23/66 (2006.01); H03F 3/195 (2006.01); H03F 1/02 (2006.01);
U.S. Cl.
CPC ...
H01L 24/20 (2013.01); H01L 23/047 (2013.01); H01L 23/3121 (2013.01); H01L 23/66 (2013.01); H01L 24/19 (2013.01); H03F 3/195 (2013.01); H01L 2223/6616 (2013.01); H01L 2224/214 (2013.01); H01L 2924/1033 (2013.01); H01L 2924/13064 (2013.01); H01L 2924/1421 (2013.01); H03F 1/0288 (2013.01); H03F 2200/451 (2013.01);
Abstract

A transistor amplifier includes a semiconductor layer structure comprising first and second major surfaces and a plurality of unit cell transistors on the first major surface that are electrically connected in parallel, each unit cell transistor comprising a gate finger coupled to a gate manifold, a drain finger coupled to a drain manifold, and a source finger. The semiconductor layer structure is free of a via to the source fingers on the second major surface.


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