logo

For the Inventor, By the Inventor

The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 12165729 B1

PDFFull Text
Date of Patent:
Dec. 10, 2024

Filed:

Jul. 01, 2022

Semiconductor device including memory cells and method for manufacturing thereof

Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Hung-Li Chiang, Taipei, TW;

Yu-Sheng Chen, Hsinchu, TW;

Chao-Ching Cheng, Hsinchu, TW;

Tzu-Chiang Chen, Hsinchu, TW;

Assignee:

TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu, TW;

Attorney:

STUDEBAKER & BRACKET PC

Primary Examiner:

Matthew C Landau

Assistant Examiner:

Dmitriy Yemelyanov

Int. Cl.
CPC ...
G11C 5/06 (2006.01); G11C 11/16 (2006.01); G11C 11/22 (2006.01); H10B 51/20 (2023.01); H10B 51/30 (2023.01); H10B 51/40 (2023.01); H10B 61/00 (2023.01); H10B 63/00 (2023.01); H10N 50/01 (2023.01); H10N 50/10 (2023.01); H10N 50/85 (2023.01); H10N 70/00 (2023.01); H10N 70/20 (2023.01);
U.S. Cl.
CPC ...
G11C 5/063 (2013.01); G11C 11/161 (2013.01); G11C 11/223 (2013.01); H10B 51/20 (2023.02); H10B 51/30 (2023.02); H10B 51/40 (2023.02); H10B 61/22 (2023.02); H10B 63/30 (2023.02); H10B 63/84 (2023.02); H10N 50/01 (2023.02); H10N 50/10 (2023.02); H10N 50/85 (2023.02); H10N 70/063 (2023.02); H10N 70/231 (2023.02); H10N 70/253 (2023.02); H10N 70/882 (2023.02); H10N 70/8833 (2023.02);
Abstract

A semiconductor device includes logic circuitry including a transistor disposed over a substrate, multiple layers each including metal wiring layers and an interlayer dielectric layer, respectively, disposed over the logic circuitry, and memory arrays. The multiple layers of metal wiring include, in order closer to the substrate, first, second, third and fourth layers, and the memory arrays include lower multiple layers disposed in the third layer.

Find Patent Forward Citations

Chiang, Hung-Li. (2024). Semiconductor device including memory cells and method for manufacturing thereof (U.S. Patent No. 12165729). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/12165729

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Loading…