The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 10, 2024

Filed:

Aug. 02, 2022
Applicant:

Renesas Electronics Corporation, Tokyo, JP;

Inventors:

Kouji Satou, Tokyo, JP;

Shunya Nagata, Tokyo, JP;

Jiro Ishikawa, Tokyo, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/419 (2006.01); G11C 11/412 (2006.01); H10B 10/00 (2023.01); G11C 11/41 (2006.01);
U.S. Cl.
CPC ...
G11C 11/419 (2013.01); G11C 11/412 (2013.01); H10B 10/12 (2023.02); H10B 10/18 (2023.02);
Abstract

A semiconductor device includes a first regulator for generating a first power supply potential, a second regulator for generating a second power supply potential lower than the first power supply potential, and a static random access memory (SRAM) having a normal operation mode and a resume standby mode. The SRAM includes power supply switching circuits receiving a first power supply potential and a second power supply potential, and a memory array including a plurality of memory cells. When the SRAM is in the normal operation mode, the power switch circuit is controlled so that the first power supply potential is supplied from the power switch circuit to the memory array, and when SRAM is in the resume standby mode, the second power supply potential is supplied from the power switch circuit to the memory array.


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