The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 10, 2024

Filed:

Oct. 11, 2018
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

John V. Arthur, Mountain View, CA (US);

Brian Taba, Cupertino, CA (US);

Rathinakumar Appuswamy, San Jose, CA (US);

Andrew S. Cassidy, San Jose, CA (US);

Pallab Datta, San Jose, CA (US);

Steven K. Esser, San Jose, CA (US);

Myron D. Flickner, San Jose, CA (US);

Jennifer Klamo, San Jose, CA (US);

Dharmendra S. Modha, San Jose, CA (US);

Hartmut Penner, San Jose, CA (US);

Jun Sawada, Austin, TX (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06N 3/08 (2023.01); G06N 3/04 (2023.01); G06N 3/063 (2023.01);
U.S. Cl.
CPC ...
G06N 3/08 (2013.01); G06N 3/04 (2013.01); G06N 3/063 (2013.01);
Abstract

Networks for distributing parameters and data to neural network compute cores. In various embodiments, a neural inference chip comprises a plurality of neural cores and at least one network interconnecting the plurality of neural cores. Each of the plurality of neural cores is adapted to apply a plurality of synaptic weights to a plurality of input activations to produce a plurality of output activations. The at least one network is adapted to simultaneously deliver synaptic weights and/or input activations to the plurality of neural cores.


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