The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 10, 2024

Filed:

Mar. 16, 2021
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Udaya Natarajan, El Dorado Hills, CA (US);

Kannappan Rajaraman, Bangalore, IN;

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 1/3215 (2019.01); G06F 1/26 (2006.01); G06F 1/3234 (2019.01); G06F 1/3287 (2019.01); G06F 1/3296 (2019.01); G06F 9/4401 (2018.01);
U.S. Cl.
CPC ...
G06F 1/3215 (2013.01); G06F 1/266 (2013.01); G06F 1/3253 (2013.01); G06F 1/3287 (2013.01); G06F 1/3296 (2013.01); G06F 9/4418 (2013.01); G06F 2213/0042 (2013.01); Y02D 10/00 (2018.01);
Abstract

A power saving apparatus and method for a host system to proactively decide to save power and increase battery life when bus powered peripheral devices are connected to the System's USB TYPE-C ports. The Host (or Host System) decides if a Bus Powered Device (BPD), hub or a peripheral device requires application services, or a device-initiated wake based on wake policies of a respective Universal Serial Bus (USB) 3.2, THUNDERBOLT 3 (TBT3), USB4, DISPLAYPORT (DP) Protocol. Thereafter, the Host decides based on S0, Low Power System standby entry—wake time latency requirement along with USB TYPE-C IO Protocol policies, to trigger the system power delivery (PD) Controller to remove power to the BPD. To save power, the Host System Wake logic power partition is also powered off.


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