The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 10, 2024

Filed:

May. 11, 2023
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu, TW;

Inventors:

Yu-Ann Lai, Hsin-Chu, TW;

Ruo-Rung Huang, Hsin-Chu, TW;

Kun-Lung Chen, Chu Pei, TW;

Chun-Yi Yang, Hsinchu, TW;

Chan-Hong Chern, Palo Alto, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G01R 31/26 (2020.01); G01R 31/27 (2006.01); H03K 3/017 (2006.01); H03K 17/687 (2006.01);
U.S. Cl.
CPC ...
G01R 31/2621 (2013.01); G01R 31/27 (2013.01); H03K 3/017 (2013.01); H03K 17/6871 (2013.01); H03K 2217/0063 (2013.01); H03K 2217/0072 (2013.01);
Abstract

An apparatus and method for testing gallium nitride field effect transistors (GaN FETs) are disclosed herein. In some embodiments, the apparatus includes: a high side GaN FET, a low side GaN FET, a high side driver coupled to a gate of the high side GaN FET, a low side driver coupled to a gate of the low side GaN FET, and a driver circuit coupled to the high side and low side drivers and configured to generate drive signals capable of driving the high and low side GaN FETs, wherein the high and low side GaN FETs and transistors, within the high and low side drivers and the driver circuit, are patterned on a same semiconductor device layer during a front-end-of-line (FEOL) process.


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