The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 03, 2024

Filed:

Mar. 29, 2023
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Yu-Chao Lin, Hsinchu, TW;

Jung-Piao Chiu, Kaohsiung, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10N 70/00 (2023.01); H10B 63/00 (2023.01);
U.S. Cl.
CPC ...
H10N 70/801 (2023.02); H10B 63/20 (2023.02); H10B 63/80 (2023.02); H10N 70/011 (2023.02);
Abstract

A memory array, a semiconductor chip and a method for forming the memory array are provided. The memory array includes first signal lines, second signal lines and memory cells. The first signal lines extend along a first direction. The second signal lines extend along a second direction over the first signal lines. The memory cells are defined at intersections of the first and second signal lines, and respectively include a resistance variable layer, a switching layer, an electrode layer and a carbon containing dielectric layer. The switching layer is overlapped with the resistance variable layer. The electrode layer lies between the resistance variable layer and the switching layer. The carbon containing layer laterally surrounds a stacking structure including the resistance variable layer, the switching layer and the electrode layer.


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