The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 03, 2024
Filed:
Sep. 14, 2022
Applicant:
United Microelectronics Corp., Hsin-Chu, TW;
Inventors:
Hui-Lin Wang, Taipei, TW;
Ching-Hua Hsu, Kaohsiung, TW;
Chen-Yi Weng, New Taipei, TW;
Jing-Yin Jhang, Tainan, TW;
Po-Kai Hsu, Tainan, TW;
Assignee:
UNITED MICROELECTRONICS CORP., Hsin-Chu, TW;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10N 50/01 (2023.01); G11C 11/16 (2006.01); H10B 61/00 (2023.01); H10N 50/10 (2023.01); H10N 50/80 (2023.01); H10N 50/85 (2023.01);
U.S. Cl.
CPC ...
H10N 50/01 (2023.02); G11C 11/161 (2013.01); H10B 61/00 (2023.02); H10N 50/10 (2023.02); H10N 50/80 (2023.02); H10N 50/85 (2023.02);
Abstract
The high-density MRAM device of the present invention has a second interlayer dielectric (ILD) layer covering the capping layer in the MRAM cell array area and the logic area. The thickness of the second ILD layer in the MRAM cell array area is greater than that in the logic area. The composition of the second ILD layer in the logic area is different from the composition of the second ILD layer in the MRAM cell array area.