The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 03, 2024
Filed:
Jun. 21, 2021
Taiwan Semiconductor Manufacturing Company Ltd., Hsinchu, TW;
Yung-Chih Tsai, Hsinchu County, TW;
Chih-Ping Chao, Hsin-Chu, TW;
Chun-Hung Chen, Hsinchu County, TW;
Shaoqiang Zhang, Hsinchu, TW;
Kuan-Liang Liu, Pingtung County, TW;
Chun-Pei Wu, Nantou County, TW;
Alexander Kalnitsky, San Francisco, CA (US);
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD., Hsinchu, TW;
Abstract
A method includes: receiving a composite substrate including a first region and a second region, the composite substrate comprising a semiconductor substrate and an insulator layer over the semiconductor substrate; bonding a silicon layer to the composite substrate; depositing a capping layer over the silicon layer; forming a trench through the capping layer, the silicon layer and the insulator layer, the trench exposing a surface of the semiconductor substrate in the first region; growing an initial epitaxial layer in the trench; removing the capping layer to form an epitaxial layer from the silicon layer and the initial epitaxial layer; forming a transistor layer over the epitaxial layer, the transistor layer including a first transistor and a second transistor in the first region and the second region, respectively; and forming an interconnect layer over the transistor layer and electrically coupling the first transistor to the second transistor.