The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 03, 2024

Filed:

Mar. 09, 2022
Applicant:

Kioxia Corporation, Tokyo, JP;

Inventors:

Satoshi Tsukiyama, Yokohama, JP;

Hideo Aoki, Yokohama, JP;

Tsukasa Konno, Yokohama, JP;

Assignee:

Kioxia Corporation, Tokyo, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/00 (2006.01); H01L 25/10 (2006.01);
U.S. Cl.
CPC ...
H01L 24/83 (2013.01); H01L 24/75 (2013.01); H01L 25/105 (2013.01); H01L 2224/75984 (2013.01); H01L 2224/75985 (2013.01); H01L 2224/75988 (2013.01); H01L 2224/83203 (2013.01); H01L 2224/83986 (2013.01); H01L 2225/06506 (2013.01); H01L 2225/0651 (2013.01); H01L 2225/06524 (2013.01); H01L 2225/06562 (2013.01); H01L 2225/1052 (2013.01); H01L 2924/1431 (2013.01); H01L 2924/1438 (2013.01);
Abstract

A method for manufacturing a semiconductor device of an embodiment, comprises a step of mounting a first semiconductor element on a board and a step of accommodating a member in which a plate-shaped member and a first adhesive layer are stacked in a collet and pressure-bonding the heated first adhesive layer on the board on which the first semiconductor element is mounted. The collet has a member having the first Young's modulus and a second member having a second Young's modulus which is lower than the first Young's modulus on a surface that accommodates the member in which the plate-shaped member and the first adhesive layer are stacked.


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