The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 03, 2024

Filed:

May. 30, 2022
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Cheng-Lung Yang, Kaohsiung, TW;

Chih-Hung Su, Hsinchu, TW;

Chen-Shien Chen, Hsinchu County, TW;

Hon-Lin Huang, Hsinchu, TW;

Kun-Ming Tsai, Hsinchu, TW;

Wei-Je Lin, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/48 (2006.01); H01L 21/48 (2006.01); H01L 23/00 (2006.01); H01L 23/528 (2006.01);
U.S. Cl.
CPC ...
H01L 23/481 (2013.01); H01L 21/4853 (2013.01); H01L 23/528 (2013.01); H01L 24/10 (2013.01); H01L 24/81 (2013.01); H01L 2224/0401 (2013.01); H01L 2224/3213 (2013.01);
Abstract

A method of forming a semiconductor device includes following steps. A first organic layer is formed to cover a first conductive layer. A first opening is formed in the first organic layer to expose a first surface of the first conductive layer. A first silicon layer is formed on a sidewall of the first opening and the first surface of the first conductive layer. A first dielectric layer is formed on the sidewall of the first opening and the first surface of the first conductive layer over the first silicon layer. By using a first mask, portions of the first silicon layer and the first dielectric layer on the first surface are simultaneously removed to expose the first surface, wherein after removing the portions of the first silicon layer and the first dielectric layer, the first dielectric layer covers a top surface of the first silicon layer.


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