The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 03, 2024

Filed:

Jan. 11, 2022
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Joonnyung Lee, Seoul, KR;

Yeongjun Kwon, Seoul, KR;

Jaeyong Shin, Hwaseong-si, KR;

Jeonghoon Ahn, Seongnam-si, KR;

Yunki Choi, Yongin-si, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 30/392 (2020.01); G06F 30/3953 (2020.01); H01L 23/528 (2006.01);
U.S. Cl.
CPC ...
G06F 30/3953 (2020.01); H01L 23/528 (2013.01);
Abstract

A method of designing an interconnect structure of a semiconductor apparatus is provided. The interconnect structure includes interconnection layers sequentially stacked on a semiconductor substrate, and each of the interconnection includes dummy metal patterns and main metal patterns. The method includes: determining a layout of the main metal patterns included in each of the plurality of interconnection layers; determining a number of interconnection layers in the plurality of interconnection layers; and determining a layout of the dummy metal patterns included in each of the plurality of interconnection layers based on the determined layout of the main metal patterns and the determined number of interconnection layers.


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