The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 26, 2024
Filed:
Jan. 25, 2022
Applicant:
Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;
Inventors:
Yu-Chao Lin, Hsinchu, TW;
Carlos H. Diaz, Los Altos Hills, CA (US);
Shao-Ming Yu, Hsinchu County, TW;
Tung-Ying Lee, Hsinchu, TW;
Assignee:
Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10N 70/20 (2023.01); H01L 23/528 (2006.01); H10B 41/10 (2023.01); H10B 61/00 (2023.01); H10B 63/00 (2023.01); H10N 70/00 (2023.01);
U.S. Cl.
CPC ...
H10N 70/231 (2023.02); H01L 23/5283 (2013.01); H10B 41/10 (2023.02); H10B 61/00 (2023.02); H10B 63/00 (2023.02); H10B 63/24 (2023.02); H10N 70/063 (2023.02); H10N 70/841 (2023.02); H10N 70/8828 (2023.02);
Abstract
Provided are a memory cell and a method of forming the same. The memory cell includes a bottom electrode, an etching stop layer, a variable resistance layer, and a top electrode. The etching stop layer is disposed on the bottom electrode. The variable resistance layer is embedded in the etching stop layer and in contact with the bottom electrode. The top electrode is disposed on the variable resistance layer. A semiconductor device having the memory cell is also provided.