The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 26, 2024

Filed:

Jul. 31, 2020
Applicant:

Semiconductor Energy Laboratory Co., Ltd., Atsugi, JP;

Inventors:

Shunpei Yamazaki, Setagaya, JP;

Hajime Kimura, Atsugi, JP;

Takanori Matsuzaki, Atsugi, JP;

Tatsuya Onuki, Atsugi, JP;

Yuki Okamoto, Isehara, JP;

Hideki Uochi, Atsugi, JP;

Satoru Okamoto, Isehara, JP;

Hiromichi Godo, Isehara, JP;

Kazuki Tsuda, Atsugi, JP;

Hitoshi Kunitake, Isehara, JP;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H10B 63/00 (2023.01); H10B 41/27 (2023.01); H10B 43/27 (2023.01);
U.S. Cl.
CPC ...
H10B 63/845 (2023.02); H10B 63/34 (2023.02);
Abstract

A highly reliable memory device is provided. On a side surface of a first conductor extending in a first direction, a first insulator, a first semiconductor, a second insulator, a second semiconductor, and a third insulator are provided in this order when seen from the first conductor side. A first region overlapping with a second conductor with the first insulator, the first semiconductor, the second insulator, the second semiconductor, and the third insulator therebetween, and a second region overlapping with a third conductor with the first insulator, the first semiconductor, the second insulator, the second semiconductor, and the third insulator therebetween are provided in the first conductor. In the second region, a fourth conductor is provided between the first insulator and the first semiconductor.


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