The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 26, 2024

Filed:

Oct. 30, 2020
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Debendra Das Sharma, Saratoga, CA (US);

Per E. Fornberg, Portland, OR (US);

Tal Israeli, Pardes-Hana-Karkur, IL;

Zuoguo Wu, San Jose, CA (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H04L 1/00 (2006.01); H03M 13/00 (2006.01); H03M 13/09 (2006.01);
U.S. Cl.
CPC ...
H04L 1/0045 (2013.01); H03M 13/09 (2013.01); H04L 1/0057 (2013.01); H04L 1/0063 (2013.01); H04L 1/007 (2013.01);
Abstract

Systems and apparatuses can include a receiver that includes port to receive a flow control unit (Flit) across a link, the link comprising a plurality of lanes. The receiver can also include error detection circuitry to determine an error in the Flit, an error counter to count a number of errors received, the error counter to increment based on an error detected in the Flit by the error detection circuitry, a Flit counter to count a number of Flits received, the Flit counter to increment based on receiving a Flit, and bit error rate logic to determine a bit error rate based on a count recorded by the error counter and a number of bits received as indicated by the Flit counter. The systems and apparatuses can apply processes to perform direct BER measurements at the receiver.


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