The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 26, 2024
Filed:
Nov. 29, 2022
Applicant:
Rambus Inc., San Jose, CA (US);
Inventors:
Panduka Wijetunga, Thousand Oaks, CA (US);
Catherine Chen, Cupertino, CA (US);
Assignee:
Rambus, Inc., San Jose, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03L 7/081 (2006.01); H03L 7/097 (2006.01);
U.S. Cl.
CPC ...
H03L 7/0814 (2013.01); H03L 7/0816 (2013.01); H03L 7/097 (2013.01);
Abstract
A phase-locked loop or delay locked loop provides a coarse alignment between an input clock and an output clock. A latch receiver circuit provides an indicator of a delay error between the input clock and the output clock. The delay error is used by a control circuit or state machine to adjust a fine delay that affects the output clock signal timing relative to the input clock signal. The fine delay is adjusted to minimize the timing difference between the output clock signal and the input clock signal.