The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 26, 2024

Filed:

Sep. 27, 2019
Applicant:

SK Hynix Nand Product Solutions Corp., San Jose, CA (US);

Inventors:

Lei Chen, Sunnyvale, CA (US);

Yogesh B. Wakchaure, Folsom, CA (US);

Aliasgar S. Madraswala, Folsom, CA (US);

Xin Guo, San Jose, CA (US);

Cole Uhlman, Vancouver, CA;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G11C 11/56 (2006.01); G06F 3/06 (2006.01); G11C 16/08 (2006.01); G11C 16/32 (2006.01);
U.S. Cl.
CPC ...
G11C 11/5642 (2013.01); G06F 3/0604 (2013.01); G06F 3/0632 (2013.01); G06F 3/064 (2013.01); G06F 3/0659 (2013.01); G06F 3/0679 (2013.01); G11C 16/08 (2013.01); G11C 16/32 (2013.01);
Abstract

A method and apparatus to reduce read retry operations in a NAND Flash memory is provided. To reduce the number of read retries for future reads, a word line group is assigned an optimal read voltage, the reference voltage that results in eliminating the read error for the word line is selected as the optimal read voltage (also referred to as a 'sticky voltage') for the word line group to be used for a next read of the page. An optimal read voltage per word line group for the page per NAND Flash memory die is stored in the lookup table. Storing an optimal read voltage per word line group instead of per die reduces the number of read retries.


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