The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 19, 2024
Filed:
Aug. 02, 2022
Globalfoundries U.s. Inc., Malta, NY (US);
Mahbub Rashed, Santa Clara, CA (US);
Irene Y. Lin, Los Altos Hills, CA (US);
Steven Soss, Cornwall, NY (US);
Jeff Kim, San Jose, CA (US);
Chinh Nguyen, Austin, TX (US);
Marc Tarabbia, Pleasant Valley, NY (US);
Scott Johnson, Wappingers Falls, NY (US);
Subramani Kengeri, San Jose, CA (US);
Suresh Venkatesan, Danbury, CT (US);
GLOBALFOUNDRIES U.S. INC., Malta, NY (US);
Abstract
A semiconductor device including four transistors. Gates of first and third transistors extend longitudinally as part of a first linear strip. Gates of second and fourth transistors extend longitudinally as part of a second linear strip parallel to and spaced apart from first linear strip. Aligned first and second gate cut isolations separate gates of first and second transistor from gates of third transistor and fourth transistor respectively. First and second CB layers connect to the gate of first transistor and second transistor respectively. CA layer extends longitudinally between first end and second end of CA layer connects to CB layers. CB layers are electrically connected to gates of first transistor adjacent first end of CA layer and second transistor adjacent second end of CA layer respectively. CA layer extends substantially parallel to first and second linear strips and is substantially perpendicular to first and second CB layers.