The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 19, 2024

Filed:

Sep. 21, 2021
Applicant:

Winbond Electronics Corp., Taichung, TW;

Inventors:

Hsin-Hung Chou, Taichung, TW;

Tsung-Wei Lin, Taichung, TW;

Kao-Tsair Tsai, Taichung, TW;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/3213 (2006.01); H01L 21/027 (2006.01); H01L 21/311 (2006.01); H01L 29/66 (2006.01); H10B 41/30 (2023.01);
U.S. Cl.
CPC ...
H01L 21/32139 (2013.01); H01L 21/0274 (2013.01); H01L 21/31138 (2013.01); H10B 41/30 (2023.02); H01L 29/6656 (2013.01);
Abstract

A method for forming a semiconductor memory structure includes sequentially forming an active layer, a hard mask layer and a core layer over a substrate, and etching the core layer to form a core pattern. The core pattern includes a first strip, a second strip, and a plurality of supporting features abutting the first and second strips. The method also includes forming a spacer layer alongside the core pattern, removing the core pattern, forming a photoresist pattern above the spacer layer, etching the hard mask layer using the photoresist pattern and the spacer layer to form a hard mask pattern, and transferring the hard mask pattern into the active layer to form a gate stack.


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