The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 19, 2024

Filed:

Mar. 09, 2023
Applicant:

Synopsys, Inc., Mountain View, CA (US);

Inventors:

Harold Pilo, Underhill, VT (US);

Anurag Garg, Cupertino, CA (US);

Assignee:

Synopsys, Inc., Sunnyvale, CA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G11C 29/00 (2006.01); G11C 11/418 (2006.01); G11C 11/419 (2006.01); G11C 29/12 (2006.01); G11C 29/38 (2006.01);
U.S. Cl.
CPC ...
G11C 29/38 (2013.01); G11C 11/418 (2013.01); G11C 11/419 (2013.01); G11C 29/12015 (2013.01);
Abstract

A method is provided for testing two port memory. The method includes receiving a synchronous write through (SWT) mode signal that indicates one of a functional mode of operation and a testing mode of operation of the memory, wherein the testing mode triggers bypassing of one or more read operations from bit cells of the memory identified by read address signals, and switching between the functional and testing modes of operation in dependence on the SWT mode signal. When the memory is in the testing mode of operation the circuit, receiving test data obtained from read address signals to represent a test state for the bit cells of the memory.


Find Patent Forward Citations

Loading…