The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 19, 2024

Filed:

Jul. 22, 2022
Applicant:

SK Hynix Inc., Icheon-si, KR;

Inventor:

Soo Yeol Chai, Icheon-si, KR;

Assignee:

SK hynix Inc., Icheon-si, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 16/34 (2006.01); G11C 16/10 (2006.01); G11C 16/26 (2006.01);
U.S. Cl.
CPC ...
G11C 16/3459 (2013.01); G11C 16/102 (2013.01); G11C 16/26 (2013.01); G11C 16/3404 (2013.01);
Abstract

A memory device may include a plurality of memory cells, a peripheral circuit configured to perform a plurality of program loops on selected memory cells among the plurality of memory cells, each of the plurality of program loops including a program pulse application operation and a program verify operation, and control logic configured to control the peripheral circuit to suspend an nprogram loop (n is a natural number equal to or greater than 1) among the plurality of program loops in response to a suspend command received during the nprogram loop, and to resume the nprogram loop with a negative verify operation in response to a resume command. The negative verify operation applies a negative voltage having a voltage less than a state voltage at the time of application of the resume command.


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