The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 19, 2024

Filed:

Sep. 21, 2022
Applicant:

Changxin Memory Technologies, Inc., Hefei, CN;

Inventor:

Zequn Huang, Hefei, CN;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G11C 11/4076 (2006.01); G06F 1/04 (2006.01); G11C 7/10 (2006.01); G11C 8/10 (2006.01); G11C 8/12 (2006.01); G11C 8/18 (2006.01); G11C 11/4063 (2006.01); G11C 11/4093 (2006.01); H03K 3/037 (2006.01); H03K 5/135 (2006.01); H03K 19/20 (2006.01); G11C 8/06 (2006.01); G11C 11/408 (2006.01);
U.S. Cl.
CPC ...
G11C 11/4076 (2013.01); G06F 1/04 (2013.01); G11C 7/10 (2013.01); G11C 7/1087 (2013.01); G11C 7/109 (2013.01); G11C 7/1093 (2013.01); G11C 8/10 (2013.01); G11C 8/12 (2013.01); G11C 8/18 (2013.01); G11C 11/4063 (2013.01); G11C 11/4093 (2013.01); H03K 3/037 (2013.01); H03K 5/135 (2013.01); H03K 19/20 (2013.01); G11C 8/06 (2013.01); G11C 11/408 (2013.01);
Abstract

A signal sampling circuit and a semiconductor memory device are provided. The signal sampling circuit includes a signal input circuit, configured to determine a to-be-processed command signal and a to-be-processed chip select signal; a mode selection circuit, configured to determine a target mode clock signal and a target mode chip select signal according to the mode selection signal; a first clock processing circuit, configured to perform sampling and logic operation on the to-be-processed chip select signal and the target mode chip select signal according to the target mode clock signal, to obtain a first chip select clock signal; a second clock processing circuit, configured to perform sampling and logic operation on the to-be-processed chip select signal and the target mode chip select signal according to the target mode clock signal, to obtain a second chip select clock signal; and a command decoding circuit, configured to determine a target command signal.


Find Patent Forward Citations

Loading…