The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 19, 2024

Filed:

Feb. 24, 2022
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Sanguk Han, Asan-si, KR;

Jaemin Jung, Seoul, KR;

Jeongkyu Ha, Hwaseong-si, KR;

Kwanjai Lee, Yongin-si, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/532 (2006.01); G09G 3/20 (2006.01); H01L 23/00 (2006.01);
U.S. Cl.
CPC ...
G09G 3/20 (2013.01); H01L 23/53209 (2013.01); H01L 23/53271 (2013.01); H01L 24/10 (2013.01); G09G 2300/0408 (2013.01); G09G 2300/0426 (2013.01);
Abstract

A chip on film package is provided. The chip on film package includes a film substrate with a base film, a conductive pad extending in a first direction on the base film, and a conductive line pattern extending from the conductive pad; a semiconductor chip provided on the film substrate; and a bump structure provided between the semiconductor chip and the conductive pad. A first peripheral wall and a second peripheral wall of the bump structure extend in the first direction and define a trench, a portion of the conductive pad is provided in the trench, and the conductive pad is spaced apart from at least one of the first peripheral wall and the second peripheral wall.


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