The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 19, 2024

Filed:

Oct. 04, 2021
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Rajkishore Barik, Santa Clara, CA (US);

Stephan A. Herhut, Santa Clara, CA (US);

Jaswanth Sreeram, San Jose, CA (US);

Tatiana Shpeisman, Menlo Park, CA (US);

Richard L. Hudson, Florence, MA (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 9/50 (2006.01); G06F 13/42 (2006.01);
U.S. Cl.
CPC ...
G06F 9/5083 (2013.01); G06F 9/505 (2013.01); G06F 13/4239 (2013.01);
Abstract

Methods, apparatus, systems, and articles of manufacture are disclosed to steal work in heterogeneous computing systems. An apparatus includes load balancing circuitry to obtain tasks from a workload by encoding minimum and maximum index ranges of a data parallel operation, allocate a first task from the workload to a first work queue based on a first capability of first computation circuitry, the first computation circuitry to process the first task in the first work queue, and allocate a second task from the workload to a second work queue, second computation circuitry to process the second task in the second work queue. The apparatus further includes first work stealer logic to steal the second task from the second work queue using an atomic operation to access the second work queue.


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