Memory operating method, memory and electronic device

Abstract

Disclosed are a memory operating method, memory and electronic device. The memory complies with a read-write parallel protocol and includes a plurality of memory banks, and the method includes: sequentially mapping read and write transactions for consecutive logical addresses to different banks according to a predetermined transmission bit width by an address decoder, and arbitrating the read transaction and write transaction mapped to the same bank in a current clock cycle by an arbitration circuit, wherein in case that a specific low address bits of the logical address are the same, the read and/or the write transaction are mapped to the same bank. The disclosure avoids long-term occupation of a certain physical bank with specific low address decoding solution, thereby improving the execution efficiency of the read-write parallel protocol. Furthermore, an arbitration mechanism is introduced to arbitrate read and write conflicts for the same memory bank in each clock cycle.