The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 19, 2024
Filed:
May. 30, 2023
Applicant:
Texas Instruments Incorporated, Dallas, TX (US);
Inventors:
David Matthew Thompson, Dallas, TX (US);
Abhijeet Ashok Chachad, Plano, TX (US);
Assignee:
TEXAS INSTRUMENTS INCORPORATED, Dallas, TX (US);
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06F 11/10 (2006.01); G06F 9/30 (2018.01); G06F 9/38 (2018.01); G06F 9/448 (2018.01); G06F 9/46 (2006.01); G06F 9/48 (2006.01); G06F 9/52 (2006.01); G06F 12/0811 (2016.01); G06F 12/0815 (2016.01); G06F 12/0879 (2016.01); G06F 12/0888 (2016.01); G06F 12/0895 (2016.01); G06F 12/128 (2016.01); G06F 13/16 (2006.01); H03M 13/15 (2006.01);
U.S. Cl.
CPC ...
G06F 11/106 (2013.01); G06F 9/30047 (2013.01); G06F 9/30101 (2013.01); G06F 9/3867 (2013.01); G06F 9/4498 (2018.02); G06F 9/467 (2013.01); G06F 9/4812 (2013.01); G06F 9/52 (2013.01); G06F 11/1064 (2013.01); G06F 11/1068 (2013.01); G06F 12/0811 (2013.01); G06F 12/0879 (2013.01); G06F 12/0895 (2013.01); G06F 13/1668 (2013.01); H03M 13/1575 (2013.01); G06F 12/0815 (2013.01); G06F 12/0888 (2013.01); G06F 12/128 (2013.01); G06F 2212/1024 (2013.01); G06F 2212/1028 (2013.01); G06F 2212/1032 (2013.01); G06F 2212/608 (2013.01);
Abstract
An apparatus includes a central processing unit (CPU) core and a cache subsystem coupled to the CPU core. The cache subsystem includes a first memory, a second memory, and a controller coupled to the first and second memories. The controller is configured to execute a sequence of scrubbing transactions on the first memory and execute a functional transaction on the second memory. One of the scrubbing transactions and the functional transaction are executed concurrently.