The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 19, 2024
Filed:
Dec. 08, 2022
Rambus Inc., San Jose, CA (US);
Aws Shallal, Cary, NC (US);
Panduka Wijetunga, Thousand Oaks, CA (US);
Rambus Inc., San Jose, CA (US);
Abstract
Disclosed are techniques for a power management integrated circuit (PMIC) to support a power-up sequence from a powered-down state to a powered-up state when both a main supply voltage and a backup supply voltage are present or when only the backup supply voltage is present. The PMIC may monitor the two supply voltages to identify the supply voltages that are present. The PMIC may be configured with a power-up initialization mode of operation through an EFUSE/MTP register, including a first bit to control power up of a voltage regulator of the PMIC with the main supply voltage or the backup supply voltage. Another bit may control power up of the voltage regulator with the backup supply voltage in the dual-supply or the single-supply configuration. The PMIC may execute one of four power-up sequences based on the monitored status of the supply voltages and the configured power-up initialization mode of operation.