The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 12, 2024

Filed:

Dec. 26, 2020
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Siddhartha Chhabra, Portland, OR (US);

Manjula Peddireddy, Santa Clara, CA (US);

Hormuzd Khosravi, Portland, OR (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H04L 9/08 (2006.01); G06F 12/14 (2006.01); G06F 13/16 (2006.01); G06F 21/64 (2013.01); G06F 21/78 (2013.01); H04L 9/32 (2006.01); H04L 9/40 (2022.01); G06F 21/72 (2013.01); G06F 21/79 (2013.01);
U.S. Cl.
CPC ...
H04L 9/3242 (2013.01); G06F 12/1408 (2013.01); G06F 13/1668 (2013.01); G06F 21/64 (2013.01); G06F 21/78 (2013.01); H04L 9/0819 (2013.01); H04L 9/0894 (2013.01); H04L 63/0428 (2013.01); H04L 63/123 (2013.01); G06F 21/72 (2013.01); G06F 21/79 (2013.01);
Abstract

In embodiments detailed herein describe an encryption architecture with fast zero support (e.g., FZ-MKTME) to allow memory encryption and integrity architecture to work efficiently with 3DXP or other far memory memories. In particular, an encryption engine for the purpose of fast zeroing in the far memory controller is detailed along with mechanisms for consistent key programming of this engine. For example, an instruction is detailed which allows software to send keys protected even when the controller is located outside of a system on a chip (SoC), etc.


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