Circuit for controlling the slew rate of a transistor

Abstract

Disclosed are circuits for controlling slew rate of a transistor during switching. Each circuit includes a first transistor (e.g., a gallium nitride (GaN)-based high electron mobility transistor (HEMT) or metal-insulator-semiconductor HEMT (MISHEMT)), a capacitor, and a second transistor. The first transistor includes a first gate connected to a pad for receiving a pulse-width modulation (PWM) signal, a first drain region connected to a first plate of the capacitor, and a first source region. The second transistor includes a second gate connected to a second plate of the capacitor, a second drain region, and a second source region and is connected to both the pad and the first transistor. The connection between the first and second transistors varies depending on whether the first transistor is an enhancement or depletion mode device and on whether the slew rate control is employed for on state or off state switching.