The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 12, 2024

Filed:

Aug. 11, 2023
Applicant:

Micron Technology, Inc., Boise, ID (US);

Inventors:

Eric N. Lee, San Jose, CA (US);

Kishore Kumar Muchherla, Fremont, CA (US);

Jeffrey S. McNeil, Nampa, ID (US);

Jung-Sheng Hoei, Newark, CA (US);

Assignee:

Micron Technology, Inc., Boise, ID (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 16/06 (2006.01); G11C 7/10 (2006.01); G11C 7/14 (2006.01); G11C 7/22 (2006.01);
U.S. Cl.
CPC ...
G11C 7/106 (2013.01); G11C 7/1057 (2013.01); G11C 7/1084 (2013.01); G11C 7/1087 (2013.01); G11C 7/14 (2013.01); G11C 7/222 (2013.01);
Abstract

Memory devices might include an array of memory cells, a plurality of access lines, and control logic. The array of memory cells includes a plurality of strings of series-connected memory cells. Each access line of the plurality of access lines is connected to a control gate of a respective memory cell of each string of series-connected memory cells of the plurality of strings of series-connected memory cells. The control logic is configured to: open the array of memory cells for multiple read operations; read first page data from respective memory cells coupled to a selected access line of the plurality of access lines; read second page data from the respective memory cells coupled to the selected access line; and close the array of memory cells subsequent to reading the first page data and the second page data.


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