The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 12, 2024
Filed:
Feb. 22, 2021
Applicant:
Southeast University, Jiangsu, CN;
Inventors:
Assignee:
SOUTHEAST UNIVERSITY, Jiangsu, CN;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06N 3/063 (2023.01); G06N 3/04 (2023.01); G06F 119/12 (2020.01);
U.S. Cl.
CPC ...
G06N 3/063 (2013.01); G06N 3/04 (2013.01); G06F 2119/12 (2020.01);
Abstract
The present invention discloses an ultralow-power negative margin timing monitoring method of a neural network circuit, relates to an adaptive voltage regulation technology based on on-chip timing detection, and belongs to the technical field of low-power design of integrated circuit. The present invention provides an ultralow-power operating method of neural network circuit. By inserting a timing monitoring unit in specific position of critical paths and setting partial circuits to operate under 'negative margin', the system can further lower voltage, compress the timing slack, and obtain higher power gain.