The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 12, 2024
Filed:
Mar. 14, 2020
Intel Corporation, Santa Clara, CA (US);
Prasoonkumar Surti, Folsom, CA (US);
Subramaniam Maiyuran, Gold River, CA (US);
Valentin Andrei, San Jose, CA (US);
Abhishek Appu, El Dorado Hills, CA (US);
Varghese George, Folsom, CA (US);
Altug Koker, El Dorado Hills, CA (US);
Mike Macpherson, Portland, OR (US);
Elmoustapha Ould-Ahmed-Vall, Chandler, AZ (US);
Vasanth Ranganathan, El Dorado Hills, CA (US);
Joydeep Ray, Folsom, CA (US);
Lakshminarayanan Striramassarma, Folsom, CA (US);
SungYe Kim, Folsom, CA (US);
Intel Corporation, Santa Clara, CA (US);
Abstract
Embodiments described herein include software, firmware, and hardware logic that provides techniques to perform arithmetic on sparse data via a systolic processing unit. One embodiment provides techniques to optimize training and inference on a systolic array when using sparse data. One embodiment provides techniques to use decompression information when performing sparse compute operations. One embodiment enables the disaggregation of special function compute arrays via a shared reg file. One embodiment enables packed data compress and expand operations on a GPGPU. One embodiment provides techniques to exploit block sparsity within the cache hierarchy of a GPGPU.