The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 12, 2024
Filed:
Dec. 18, 2020
Intel Corporation, Santa Clara, CA (US);
Deepak S Kirubakaran, Hillsboro, OR (US);
Ramakrishnan Sivakumar, Hillsboro, OR (US);
Russell Fenger, Beaverton, OR (US);
Monica Gupta, Hillsboro, OR (US);
Jianwei Dai, Portland, OR (US);
Premanand Sakarda, Acton, MA (US);
Guy Therien, Beaverton, OR (US);
Rajshree Chabukswar, Sunnyvale, CA (US);
Chad Gutierrez, Santa Clara, CA (US);
Renji Thomas, Hillsboro, OR (US);
Intel Corporation, Santa Clara, CA (US);
Abstract
A hardware and software coordinated processor power state policy (e.g., policy for C-state) that delivers optimal power state selection by taking in to account the performance and/or responsiveness needs of thread expected to be scheduled on the core entering idle, to achieve improved IPC and performance for cores running user critical tasks. The scheme provides the ability to deliver responsiveness gains for important and/or user-critical threads running on a system-on-chip. A power management controller coupled to the plurality of processing cores, wherein the power management controller receives a hint from an operating system indicative of a bias towards a power state or performance state for at least one of the processing cores of the plurality of processing cores based on a priority of a thread in context switch.