The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 05, 2024

Filed:

Aug. 15, 2023
Applicant:

Kepler Computing Inc., San Francisco, CA (US);

Inventors:

Sasikanth Manipatruni, Portland, OR (US);

Rajeev Kumar Dokania, Beaverton, OR (US);

Ramamoorthy Ramesh, Moraga, CA (US);

Gaurav Thareja, Santa Clara, CA (US);

Amrita Mathuriya, Portland, OR (US);

Assignee:

Kepler Computing Inc., San Francisco, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10B 53/30 (2023.01); G11C 11/22 (2006.01); H01L 49/02 (2006.01);
U.S. Cl.
CPC ...
H10B 53/30 (2023.02); G11C 11/221 (2013.01); H01L 28/56 (2013.01);
Abstract

Approaches for integrating FE memory arrays into a processor, and the resulting structures are described. Simultaneous integrations of regions with ferroelectric (FE) cells and regions with standard interconnects are also described. FE cells include FE capacitors that include a FE stack of layers, which is encapsulated with a protection material. The protection material protects the FE stack of layers as structures for regular logic are fabricated in the same die.


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