The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 05, 2024
Filed:
Aug. 08, 2022
Applicant:
Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;
Inventors:
Assignee:
TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., Hsin-Chu, TW;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/66 (2006.01); H01L 21/28 (2006.01); H01L 21/8234 (2006.01); H01L 29/51 (2006.01); H01L 21/3105 (2006.01); H01L 21/311 (2006.01);
U.S. Cl.
CPC ...
H01L 21/823437 (2013.01); H01L 21/28123 (2013.01); H01L 21/823431 (2013.01); H01L 29/66545 (2013.01); H01L 29/66795 (2013.01); H01L 21/28088 (2013.01); H01L 21/31058 (2013.01); H01L 21/31144 (2013.01); H01L 29/517 (2013.01);
Abstract
A semiconductor device structure is provided. The device includes a dielectric layer over a substrate. The substrate has a fin structure, and the dielectric layer has a trench exposing a portion of the fin structure. The includes a gate material layer in the trench. The gate material has a topmost surface that is highly planar.
Chang, Chai-Wei. (2024). Method for forming semiconductor device structure with gate and resulting structures (U.S. Patent No. 12136572). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/12136572
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile